The present invention relates generally to reducing power in integrated circuits that include high-voltage switches, and more particularly to reducing power consumed in bit sampling switches in high-voltage SAR ADCs (successive approximation register analog-to-digital converters).
For example, in conventional high-voltage 16-bit SAR ADCs, each bit switching circuit includes three high-voltage switches, one for sampling a high-voltage analog input signal VSIG, one for switching the bottom plate of a corresponding CDAC (capacitor DAC) capacitor to a first reference voltage VREF, and one for switching the plate of a corresponding CDAC capacitor to a second reference voltage GND. The high power consumption is due to the high dynamic power associated with the level-shifting of various digital control signals during each switching event. Furthermore, the bit switches typically are very large, in order to achieve the low channel resistances required for fast signal settling.
“Prior Art” FIG. 1A shows the basic part of a conventional 16-bit SAR ADC circuit, which is repeated for every capacitor of the CDAC array. The complete circuit includes 16 low-voltage (e.g., 5 volt) combinational logic circuits 12 which receive a sampling signal SMPL from a digital control circuit (e.g., circuit 21 in FIG. 2B), 16 signals BIT that are sequentially generated by SAR logic circuitry (e.g., SAR logic 27 in FIG. 2C) in response to the output of a SAR comparator 25, and 16 “trim” signals e.g., (BIT_SAMP in FIG. 2A) that determine which of 16 CDAC capacitors are to be utilized for sampling the analog input signal VSIG. Each of the 16 combinational logic circuits 12 generates corresponding low-voltage drive signals SIG_DRV, REF_DRV, and GND_DRV which are applied to the inputs of three corresponding level shifter circuits, respectively, in each of 16 blocks 14 in order to generate the corresponding high corresponding voltage signals HV_SIG_DRV, HV_REF_DRV, and HV_GND_DRV, respectively.
Bit switching circuit 17 in each block 14 includes three high-voltage bit switching circuits, one for each bit of the SAR ADC. For convenience, each bit switching circuit is represented by a single pole, triple throw switch having its pole terminal coupled by conductor 28 to the bottom plate of a corresponding CDAC capacitor in a CDAC 20. Each single pole, triple throw switch has one pole connected to high-voltage analog input signal VSIG, another pole connected to reference voltage VREF, and a third pole connected to the ground voltage GND (or VSS). The upper plate of each of the 16 CDAC capacitors in block 20 is connected by a conductor 24 to one input of a SAR comparator 25, the output of which is connected to an input of the above mentioned SAR logic (not shown). The three level shifter circuits in each block 14 are powered by relatively high supply voltages HVDD and HVSS, which may be 15 volts and −15 volts, respectively. The foregoing conventional SAR ADC circuitry is included in the assignee's presently marketed ADS8556 product.
All of the VSIG sampling, VREF and GND switches are formed from high-voltage transistors because they share the same “pole node” with the high-voltage analog input signal VSIG, and consequently the digital control signals SIG_DRV, REF_DRV, and GND_DRV must be level-shifted to a high voltage range. Unfortunately, the level shifters consume a great deal of power.
The problem of high power consumption in bit switches of conventional high-voltage SAR ADCs sometimes has been dealt with by using a resistive divider circuit to attenuate the high-voltage analog input signal VSIG before it is sampled onto a selected CDAC bit capacitor (or capacitors) will, to avoid the use of high-voltage switches for sampling the high-voltage analog input signal VSIG during sampling operation and switching between VREF and GND during successive approximation analog-to-digital conversion. This approach is shown in Prior Art FIG. 1B, which is the same as FIG. 1 of U.S. Pat. No. 6,731,232 entitled “Programmable Input Range in SAR ADC” issued May 4, 2004 to Kearney. The resistive divider results in an undesirably low impedance input, and also results in high power consumption in circuitry required for driving the resistive divider. Another technique for dealing with the high power consumption has been to use a capacitive divider circuit to attenuate the high-voltage input signal between the capacitors of a separate sampling CDAC in series with the conversion CDAC involved in the successive approximation operation. The capacitive divider referred to is shown in Prior Art FIG. 1C, which is the same as FIG. 6 in the above mentioned Kearney patent. In Prior Art FIG. 1C, the sampling switches used for sampling the high-voltage analog input signal onto the CDAC capacitors need to be high-voltage switches, but the VREF and GND switches used during the conversion operation can be low-voltage switches. However, this technique has the disadvantage of poor SNR (signal to noise ratio) due to the attenuation of the input signal caused by the additional sampling CDAC, as well as the disadvantage of requiring additional integrated circuit die area.
Thus, there is an unmet need for a high-voltage SAR ADC in which dynamic power consumption is substantially reduced compared to the dynamic power consumption in the closest prior art high-voltage SAR ADCs.
There also is an unmet need for a high-voltage SAR ADC having lower power consumption and requiring less integrated circuit chip area than the closest prior art high-voltage SAR ADCs.
There also is an unmet need for a high-voltage SAR ADC having reduced current spikes in the high-voltage supplies than is the case for the closest prior art high-voltage SAR ADCs.
There also is an unmet need for a high-voltage SAR ADC in which a high-voltage analog input signal can be coupled to the CDAC capacitors thereof with less signal distortion than in the closest prior art high-voltage SAR ADCs.
There also is an unmet need for a high-voltage SAR ADC having good signal-to-noise performance along with significantly lower dynamic power consumption compared to the closest prior art SAR ADCs.